Enhanced low precision binary floating-point formatting
US10656913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49968
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.