Patent · US Active

Efficient FPGA multipliers

US10656915B2 · kind B2 · utility

1Cited by

8References

20Claims

0Family size

Assignee

Achronix Semiconductor Corporation · US

Inventors

Daniel Pugh · Los Gatos, US
Raymond Nijssen · San Jose, US

Key dates

Filing date	Sep 18, 2018
Grant date	May 19, 2020
Priority date	—
Expiry date	Sep 18, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17728
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.