Inventor · Los Gatos, CA, US

Daniel Pugh

23Patents
7h-index
10Co-inventors
66Inventor score

Filing activity: Oct 27, 2000 → Jun 13, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7372297B1 Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources Electricity 46 Active
US7587697B1 System and method of mapping memory blocks in a configurable integrated circuit Physics 23 Active
US7971172B1 IC that efficiently replicates a function to save logic and routing resources Electricity 15 Active
US10790830B1 Fused memory and arithmetic circuit Electricity 12 Active
US6801052B2 Field programmable gate array core cell with efficient logic packing Physics 8 Expired
US7930666B1 System and method of providing a memory hierarchy Physics 8 Active
US8463836B1 Performing mathematical and logical operations in multiple sub-cycles Physics 7 Active
US6834291B1 Gold code generator design Physics 6 Expired
US7818361B1 Method and apparatus for performing two's complement multiplication Electricity 5 Active
US11288220B2 Cascade communications between FPGA tiles Physics 4 Active
US7765249B1 Use of hybrid interconnect/logic circuits for multiplication Electricity 4 Active
US11256476B2 Multiple mode arithmetic circuit Emerging Cross-Sectional Technologies 3 Active
US7009421B2 Field programmable gate array core cell with efficient logic packing Physics 3 Expired
US11650792B2 Multiple mode arithmetic circuit Emerging Cross-Sectional Technologies 2 Active
US8434045B1 System and method of providing a memory hierarchy Physics 2 Active
US6904105B1 Method and implemention of a traceback-free parallel viterbi decoder Electricity 1 Expired
US10656915B2 Efficient FPGA multipliers Electricity 1 Active
US11734216B2 Cascade communications between FPGA tiles Physics 1 Active
US7080107B2 Gold code generator design Physics 1 Expired
US12141088B2 Cascade communications between FPGA tiles Physics 0 Active
US12014150B2 Multiple mode arithmetic circuit Emerging Cross-Sectional Technologies 0 Active
US10963221B2 Efficient FPGA multipliers Electricity 0 Active
US12034446B2 Fused memory and arithmetic circuit Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.