Circuit generation based on zero wire load assertions
US10657211B2 · kind B2 · utility
1Cited by
5References
20Claims
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Aug 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.