Inventor · Hod HaSharon, IL

Ofer Geva

13Patents
1h-index
22Co-inventors
46Inventor score

Filing activity: May 25, 2017 → Feb 15, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US10831958B2 Integrated circuit design with optimized timing constraint configuration Physics 2 Active
US10657211B2 Circuit generation based on zero wire load assertions Physics 1 Active
US10572613B2 Estimating timing convergence using assertion comparisons Physics 1 Active
US10997737B2 Method and system for aligning image data from a vehicle camera Physics 1 Active
US11797740B2 Even apportionment based on positive timing slack threshold Physics 0 Active
US11030367B2 Out-of-context feedback hierarchical large block synthesis (HLBS) optimization Physics 0 Active
US11775730B2 Hierarchical large block synthesis (HLBS) filling Physics 0 Active
US10325045B2 Estimating timing convergence using assertion comparisons Physics 0 Active
US10568203B2 Modifying a circuit design Physics 0 Active
US11296093B2 Deep trench capacitor distribution Electricity 0 Active
US12367331B2 Approach to child block pinning Physics 0 Active
US10546092B2 Modifying a circuit design based on pre-routed top level design Physics 0 Active
US10885245B1 Out-of-context feedback hierarchical large block synthesis (HLBS) optimization General 0 Revoked

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.