Apparatus and methods to provide power management for memory devices
US10658012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.