Pattern fidelity enhancement with directional patterning technology
US10658184B2 · kind B2 · utility
6Cited by
13References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Apr 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.