Platen for reducing particle contamination on a substrate and a method thereof
US10658207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6875
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.