Methods for fabricating finFET devices having gate spacers on field insulating layers
US10658249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Oct 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.