Integrated circuit substrate and method of making
US10658281B2 · kind B2 · utility
1Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.