Marcel Wall
12Patents
1h-index
37Co-inventors
46Inventor score
Filing activity: Sep 22, 2017 → Sep 23, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10658281B2 | Integrated circuit substrate and method of making | Electricity | 1 | Active |
| US11445616B2 | Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures | Electricity | 0 | Active |
| US11177234B2 | Package architecture with improved via drill process and method for forming such package | Electricity | 0 | Active |
| US12349282B2 | Capacitors in through glass vias | Electricity | 0 | Active |
| US12159825B2 | Dielectric-to-metal adhesion promotion material | Electricity | 0 | Active |
| US12416093B2 | Electroless plating process | Electricity | 0 | Active |
| US12057252B2 | Electronic substrates having embedded inductors | Electricity | 0 | Active |
| US11291122B2 | Apparatus with a substrate provided with plasma treatment | Electricity | 0 | Active |
| US11177232B2 | Circuit device with monolayer bonding between surface structures | Electricity | 0 | Active |
| US11694898B2 | Hybrid fine line spacing architecture for bump pitch scaling | Electricity | 0 | Active |
| US11501967B2 | Selective metal deposition by patterning direct electroless metal plating | Electricity | 0 | Active |
| US12033930B2 | Selectively roughened copper architectures for low insertion loss conductive features | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.