Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
US10658337B2 · kind B2 · utility
34Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.