Vertically stacked multichip modules
US10658342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2019 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, a method for producing a circuit assembly can include coupling a first side of a first semiconductor die with a first side of a first substrate and a first side of a second substrate, the first substrate having a first electrically isolated metal layer disposed on a second side. The method can also include coupling a first side of a second semiconductor die with a second side of the second substrate and a first side of a third substrate, the third substrate having a second electrically isolated metal layer disposed on a second side. The method can further include coupling at least one conductive connector between the second substrate and the third substrate, the at least one conductive connector electrically coupling the second substrate with the third substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.