Memory device
US10658480B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1438
Abstract
A memory device includes plural electrode layers stacked in a first direction, a semiconductor layer interacting with the plural electrode layers and extending in the first direction, a first insulating film provided between the semiconductor layer and at least one electrode layer and extending along the semiconductor layer in the first direction, and a charge trapping film provided between the electrode layer and the first insulating film. The memory device further includes a second insulating film provided between the charge trapping film and the first insulating film and in contact with the first insulating film. In a flat band state, the charge trapping film has a first trap level located at a level deeper than a conduction band of the semiconductor layer and the second insulating film has a second trap level that is closer to the conduction band of the semiconductor layer than the first trap level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.