Multi-level clock and data recovery circuit
US10659214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2017 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2601
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.