Patent · US Active

Method and apparatus for automatic switch to retention mode based on architectural clock gating

US10664006B2 · kind B2 · utility

1Cited by

3References

17Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Bharat Kumar Rangarajan · Bengaluru, IN
Rakesh Misra · Bengaluru, IN
Rajesh Arimilli · Bengaluru, IN

Key dates

Filing date	Jan 11, 2018
Grant date	May 26, 2020
Priority date	—
Expiry date	Jul 29, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.