Rajesh Arimilli
8Patents
2h-index
12Co-inventors
40Inventor score
Filing activity: Jun 16, 2017 → Mar 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10691195B2 | Selective coupling of memory to voltage rails based on operating mode of processor | Emerging Cross-Sectional Technologies | 5 | Active |
| US11689203B1 | Method and apparatus for symmetric aging of clock trees | Electricity | 2 | Active |
| US10664006B2 | Method and apparatus for automatic switch to retention mode based on architectural clock gating | Emerging Cross-Sectional Technologies | 1 | Active |
| US10346574B2 | Effective substitution of global distributed head switch cells with cluster head switch cells | Electricity | 1 | Active |
| US10466766B2 | Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexers | Emerging Cross-Sectional Technologies | 1 | Active |
| US11604505B2 | Processor security mode based memory operation management | Physics | 0 | Active |
| US11493986B2 | Method and system for improving rock bottom sleep current of processor memories | Emerging Cross-Sectional Technologies | 0 | Active |
| US11169593B2 | Selective coupling of memory to voltage rails for different operating modes | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.