Memory device including page buffers
US10664395B2 · kind B2 · utility
3Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.