Automatic pipelining of memory circuits
US10664561B1 · kind B1 · utility
4Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Oct 10, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.