Patent · US Active

Processor with memory array operable as either cache memory or neural network unit memory

US10664751B2 · kind B2 · utility

13Cited by

6References

10Claims

0Family size

Assignee

VIA ALLIANCE SEMICONDUCTOR CO., LTD. · CN

Inventors

G. Glenn Henry · Austin, US
Douglas R. Reed · Austin, US

Key dates

Filing date	Dec 1, 2016
Grant date	May 26, 2020
Priority date	—
Expiry date	May 9, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/2515
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.