Static random-access memory with virtual banking architecture, and system and method including the same
US10665295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Nov 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.