Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same
US10665581B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2019 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.