IC with top side capacitor having lateral regions with thinned capacitor dielectric

US10665663B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Poornika Fernandes · Sachse, US
• Bhaskar Srinivasan · Boise, US
• Guruvayurappan Mathur · Plano, US
• Abbas Ali · Plano, US
• David M. Curran · Dublin, IE
• Neil Gardner · McKinney, US

Key dates

• Filing date: Nov 21, 2018
• Grant date: May 26, 2020
• Expiry date: Nov 21, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31116
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.