Interface for parallel configuration of programmable devices
US10666265B2 · kind B2 · utility
5Cited by
2References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.