Inventor · Piedmont, CA, US

Scott J. Weber

50Patents
5h-index
61Co-inventors
67Inventor score

Filing activity: May 25, 2016 → Feb 26, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9584130B1 Partial reconfiguration control interface for integrated circuits Electricity 16 Active
US10833679B2 Multi-purpose interface for configuration data and user fabric data Electricity 15 Active
US11556677B2 Scalable runtime validation for on-device design rule checks Electricity 8 Active
US11651111B2 Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA Electricity 7 Active
US10223014B1 Maintaining reconfigurable partitions in a programmable device Physics 7 Active
US10666265B2 Interface for parallel configuration of programmable devices Electricity 5 Active
US10824500B1 Systems and methods for verifying vehicle identification number (VIN) Physics 4 Active
US11487445B2 Programmable integrated circuit with stacked memory die for storing configuration data Emerging Cross-Sectional Technologies 2 Active
US9941867B1 Circuit and method for universal pulse latch Electricity 2 Active
US11625245B2 Compute-in-memory systems and methods Physics 1 Active
US11101804B2 Fast memory for programmable devices Electricity 1 Active
US11557541B2 Interconnect architecture with silicon interposer and EMIB Electricity 1 Active
US10423747B2 Method and apparatus for supporting temporal virtualization on a target device Physics 1 Active
US11562101B2 On-device bitstream validation Electricity 1 Active
US11424744B2 Multi-purpose interface for configuration data and user fabric data Electricity 1 Active
US11822959B2 Methods and systems for processing requests using load-dependent throttling Physics 0 Active
US10394990B1 Initial condition support for partial reconfiguration Physics 0 Active
US12413232B2 Multi-purpose interface for configuration data and user fabric data Electricity 0 Active
US11901299B2 Interconnect architecture with silicon interposer and EMIB Electricity 0 Active
US11611518B2 System-in-package network processors Electricity 0 Active
US11916811B2 System-in-package network processors Electricity 0 Active
US12346489B2 Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA Electricity 0 Active
US12347783B2 Interconnect architecture with silicon interposer and EMIB Electricity 0 Active
US11901896B2 Soft network-on-chip overlay through a partial reconfiguration region Electricity 0 Active
US11334263B2 Configuration or data caching for programmable logic device Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.