Semiconductor test device and manufacturing method thereof
US10670641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2017 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.