Memory hierarchy to transfer vector data for operators of a directed acyclic graph
US10671401B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.