Memory device comprising status circuit and operating method thereof
US10671464B2 · kind B2 · utility
0Cited by
15References
19Claims
0Family size
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Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.