Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
US10671781B2 · kind B2 · utility
0Cited by
52References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.