No miss cache structure for real-time image transformations with multiple LSR processing engines
US10672368B2 · kind B2 · utility
3Cited by
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19Claims
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Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.