Methods and systems for performing decoding in finFET based memories
US10672443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Oct 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.