Production of semiconductor regions in an electronic chip
US10672644B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0179
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.