Inventor · La Penne-sur-Huveaune, FR

Franck Julien

13Patents

0h-index

14Co-inventors

37Inventor score

Filing activity: Feb 14, 2018 → Mar 29, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US12125899B2	MOS transistor having substantially parallelepiped-shaped insulating spacers	Electricity	0	Active
US11640921B2	Process for fabricating an integrated circuit comprising a phase of forming trenches in a substrate and corresponding integrated circuit	Electricity	0	Active
US11522057B2	Method for manufacturing an electronic device	Electricity	0	Active
US10930757B2	Method of manufacturing MOS transistor spacers	Electricity	0	Active
US10672644B2	Production of semiconductor regions in an electronic chip	Electricity	0	Active
US12198973B2	Integrated circuit comprising trenches formed in a substrate	Electricity	0	Active
US10332808B2	Device comprising multiple gate structures and method of simultaneously manufacturing different transistors	Electricity	0	Active
US10777552B2	Method of simultaneous fabrication of SOI transistors and of transistors on bulk substrate	Electricity	0	Active
US10553499B2	Production of semiconductor regions in an electronic chip	Electricity	0	Active
US11121042B2	Production of semiconductor regions in an electronic chip	Electricity	0	Active
US11424342B2	Fabrication process comprising an operation of defining an effective channel length for MOSFET transistors	Electricity	0	Active
US11183505B2	Process for fabricating medium-voltage transistors and corresponding integrated circuit	Electricity	0	Active
US11817484B2	Method for manufacturing an electronic device	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.