Patent · US Active

Method of fabricating ferroelectric field-effect transistor

US10672894B2 · kind B2 · utility

2Cited by

4References

20Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Jan Van Houdt · Bekkevoort, BE
Hanns Christoph Adelmann · Wilsele, BE
Han-Chung Lin · Hsinchu, TW

Key dates

Filing date	Dec 11, 2018
Grant date	Jun 2, 2020
Priority date	—
Expiry date	Dec 11, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D99/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.