Wafer-level package with enhanced performance

US10676348B2 · kind B2 · utility

Assignee

• Qorvo US, Inc. · US

Inventors

• Julio C. Costa · Oak Ridge, US
• Jon Chadwick · Greensboro, US
• David Jandzinski · Greenville, US
• Merrill Albert Hatcher, Jr. · Greensboro, US
• Jonathan Hale Hammond · Oak Ridge, US

Key dates

• Filing date: May 22, 2017
• Grant date: Jun 9, 2020
• Expiry date: May 22, 2037

Classification

• Technology area (CPC —): General

Abstract

The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.