Jon Chadwick
46Patents
5h-index
13Co-inventors
66Inventor score
Filing activity: Aug 4, 1995 → Dec 4, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9613831B2 | Encapsulated dies with enhanced thermal performance | Electricity | 201 | Active |
| US10882740B2 | Wafer-level package with enhanced performance and manufacturing method thereof | Electricity | 72 | Active |
| US5581132A | Peak demand limiter and sequencer | Emerging Cross-Sectional Technologies | 35 | Expired |
| US10773952B2 | Wafer-level package with enhanced performance | Electricity | 14 | Active |
| US9960145B2 | Flip chip module with enhanced properties | Electricity | 13 | Active |
| US10020206B2 | Encapsulated dies with enhanced thermal performance | Electricity | 1 | Active |
| US10486963B2 | Wafer-level package with enhanced performance | Electricity | 1 | Active |
| US11069590B2 | Wafer-level fan-out package with enhanced performance | Electricity | 1 | Active |
| US9929125B2 | Flip chip module with enhanced properties | General | 0 | Revoked |
| US10804246B2 | Microelectronics package with vertically stacked dies | Electricity | 0 | Active |
| US10964672B2 | Microelectronics package with vertically stacked dies | General | 0 | Revoked |
| US10676348B2 | Wafer-level package with enhanced performance | General | 0 | Revoked |
| US10377627B2 | Wafer-level package with enhanced performance | General | 0 | Revoked |
| US10679918B2 | Wafer-level package with enhanced performance | General | 0 | Revoked |
| US10453765B2 | Wafer-level packaging for enhanced performance | General | 0 | Revoked |
| US10109550B2 | Wafer-level package with enhanced performance | Electricity | 0 | Active |
| US9576822B2 | Encapsulated dies with enhanced thermal performance | General | 0 | Revoked |
| US10442684B2 | Wafer-level package with enhanced performance | General | 0 | Revoked |
| US10622271B2 | Wafer-level packaging for enhanced performance | General | 0 | Revoked |
| US9997376B2 | Encapsulated dies with enhanced thermal performance | General | 0 | Revoked |
| US10600711B2 | Wafer-level package with enhanced performance | General | 0 | Revoked |
| US10658259B2 | Wafer-level packaging for enhanced performance | General | 0 | Revoked |
| US9892937B2 | Encapsulated dies with enhanced thermal performance | General | 0 | Revoked |
| US11011498B2 | Microelectronics package with vertically stacked dies | General | 0 | Revoked |
| US9899350B2 | Flip chip module with enhanced properties | General | 0 | Revoked |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.