Ordering memory requests based on access efficiency
US10678478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.