CPU security mechanisms employing thread-specific protection domains
US10678700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2016 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Jul 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor includes an instruction processing pipeline that interfaces to a hierarchical memory system employing an address space. The instruction processing pipeline includes execution logic that executes at least one thread in different protection domains over time, wherein the different protection domains are defined by descriptors each including first data specifying a memory region of the address space employed by the hierarchical memory system and second data specifying permissions for accessing the associated memory region. The address space can be a virtual address space or a physical address space. The protection domains can be associated with different turfs each representing a collection of descriptors. A given thread can execute in a particular protection domain(turf), one protection domain (turf) at a time with the particular protection domain (turf) selectively configured to change over time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.