Performance aware word line under-drive read assist scheme for high density SRAM to enable low voltage functionality
US10679694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2019 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Jan 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and controlled by a temperature compensation signal produced at an intermediate node between weak pull-up and strong pull-down PMOS transistors that are connected in series between VDD and VSS and respectively controlled by VDD and VSS during read operations. This configuration generates the temperature compensation signal at a level closer to VSS at high temperatures than at low temperatures, whereby write-ability is not impacted by the read-assist circuit at low temperature. An optional actuation circuit disables the temperature compensation circuit during non-active cycles to prevent current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.