Semiconductor device and method for manufacturing the same
US10680120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Apr 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.