Techniques and circuits for time-interleaved injection locked voltage controlled oscillators with jitter accumulation reset
US10680585B2 · kind B2 · utility
6Cited by
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17Claims
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Key dates
| Filing date | Apr 9, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B2201/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.