Patent · US Active

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

US10680600B2 · kind B2 · utility

20Cited by
128References
30Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 5, 2019
Grant dateJun 9, 2020
Priority date
Expiry dateApr 5, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/675
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.