Phase-locked loop monitor circuit
US10680627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.