Post-compile cache blocking analyzer
US10684833B2 · kind B2 · utility
0Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.