Data prefetching that stores memory addresses in a first table and responsive to the occurrence of loads corresponding to the memory addresses stores the memory addresses in a second table

US10684857B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wolfgang Gellerich · Eppelheim, DE
• Gerrit Koch · Herrenberg, DE
• Peter M. Held · Renningen, DE
• Martin Schwidefsky · Eppelheim, DE

Key dates

• Filing date: Feb 1, 2018
• Grant date: Jun 16, 2020
• Expiry date: Apr 14, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6028
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.