Sparse matrix multiplication using a single field programmable gate array module
US10685082B2 · kind B2 · utility
17Cited by
4References
15Claims
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Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.