Computationally efficient nano-scale conductor resistance model
US10685163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Aug 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each volume element n in the conducting structure. Furthermore, the local resistivity ρn for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wn and height Hn of the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity ρn for each of the volume elements n in the plurality of volume elements in the conducting structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.