Semiconductor memory device
US10685689B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Jan 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.