Circuit including efficient clocking for testing memory interface
US10685730B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.