Semiconductor integrated circuit fabrication with pattern-reversing process
US10685846B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2014 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30625
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.